Where quantum tunneling imposes limitations on the achievable size, speed and current of conventional metal-oxide semiconductor field-effect transistors (MOSFET), this phenomenon can be turned to an advantage in the more recently introduced tunnel FET (TFET). In such TFET, the device switches state by altering the probability of charge tunneling through a high energy barrier, as opposed to the raising or lowering of the energy barrier as is known in MOSFETs.
In a TFET, semiconducting material is arranged in p-i-n or n-i-p configuration, e.g. a sequence of a positively doped, intrinsic and negatively doped regions. The intrinsic channel may have substantially equal amounts of free electrons and holes, which corresponds to a maximum of resistivity of the semiconductor material, and thus provides a thick energy barrier. In general, the intrinsic channel may not be exactly charge carrier neutral, and may even be lightly doped, but the intrinsic channel typically has a dopant concentration substantially smaller than the positively and negatively doped regions, e.g. at least one order of magnitude smaller, such that a sufficient energy barrier between the p+ and n+ regions is imposed. By applying a voltage to the transistor gate, an overlap between the conduction band in the source and the valence band in the channel is created or enlarged, such that a tunneling window is opened. Unlike what happens in a MOSFET, in a TFET the charges move between conduction and valence bands. Creating the overlap in bands typically requires much smaller voltages than in a MOSFET.
FinFET devices were proposed as a solution to short channel effects which were major road blocks for scaling of the CMOS technology. Being three-dimensional devices, they offer additional benefit in terms of higher current in small device volume. This allows high density packing of integrated circuits. Nevertheless, FinFETs being a 3D variant of a 2D MOSFET, their sub-threshold swing is limited, e.g. to 60 mV/decade, which may form a road block for scaling of the power supply. Tunnel Field Effect transistors are an attractive solution to this problem due to their promise to offer sub-threshold swings below 60 mV/decade at room temperature.
It has been shown in literature that tunneling efficiency of TFETs can be improved by aligning tunneling direction to the gate electric field. This class of TFETs may be referred to as line-TFETs or area tunneling devices, as the current may be substantially proportional to the area of the gate or to the area of the gate overlap on the source.
A three-dimensional TFET device comprising a fin-like structure was disclosed in WO 2012/152762. The fin-like structure in a TFET device according to WO 2012/152762 may either form a source region or alternatively a channel region. A large tunneling area for band-to-band tunneling is achieved by placing the gate structure on one side and the source region on the other, preferably opposing, side of the thin fin such that a large area is available for band-to-band tunneling which strongly increases the ON-current of the device. According to WO 2012/152762, the source region may be formed to one side of the fin-like structure and the drain region may be on the other side, taken along the longitudinal direction, of the fin-like structure.